In order to explain the background of the invention, reference will be particularly made to FIG. 1.
In a conventional device for testing a semiconductor device shown in FIG. 1, there are provided measuring circuits 1 for conducting a function measurement, wherein the number of the circuits 1 is equal to the number of the input/output pins of a semiconductor device 2. There are further provided several precision measurement units 3 (hereinafter referred to as "PMU") for measuring DC characteristics (electric characteristics).
In the measuring circuit 1, the numeral 4 designates a driver circuit for supplying a variable DC voltage to a pat (pin) of the semiconductor device 2. The numeral 5 designates a comparator for comparing the output voltage from a pat of the semiconductor device 2 and a reference voltage. The numeral 6 designates a diode bridge circuit for supplying a variable current to a pin of the semiconductor device 2. The numerals 7 and 8 designate constant current sources connected to the diode bridge circuit 6, provided above and below thereof, respectively. The numeral 9 designates a voltage value register for storing the output voltage of the driver circuit 4. The numerals 10 and 12 designate current value registers for storing the output current of the diode bridge circuit 6. The numeral 54 designates a constant voltage source intended to supply a reference voltage to the diode bridge circuit 6. The numeral 11 designates a register intended to store the reference voltage of the diode bridge circuit 6. The numeral 13 designates a reference voltage value register for supplying a reference voltage to the comparator 5. The numeral 14 designates a contact element for connecting the input and/or output terminals of the circuits 4 to 6 to a pat of the semiconductor device 2.
FIG. 2(a) shows a test pattern 15 in accordance with which the semiconductor device testing device conducts a measuring operation. FIG. 2(b) shows the test pattern 15 in detail. In FIG. 2(b) the pattern "PAT" means a logical verification of a semiconductor device 2, and address numbers for the "PAT" are successively written in. The numeral at the right of each "PAT" address shows the logical level to be applied to the pin or the logical level to be obtained from the pin. Beyond the pattern, a control sentence showing the characteristics of the PAT pattern, such as, a loop instruction instructing to repeat the operation in the pattern, or a jump instruction is described. The numerals in parenthesis are those for designating the address of "I/O" pattern, "MASK" pattern, and "HIZ" pattern, respectively, and the "TM" is a description for calling out the timing of outputting the "0", "1" of the "PAT", that is, an information for making a waveform.
The pattern "I/O" is an input/output pin information of the semiconductor device 2 which is used to designate pins at which the bit is standing as the input pins, and to designate the other pins as the output pins. The pattern "MASK" is information representing pins to be measured, and only pins at which the bit is standing are those to be measured. The pattern "HIZ" is an information representing pins being in a high impedance state.
The operation of the device will be described in the following.
In the logical verification of the semiconductor device 2, it is necessary to check whether voltages having the waveforms shown in FIG. 4(b) are obtained or not at the output pins 3 and 4 when voltages having the waveforms shown in FIG. 4(a) are input to the input pins 1 or 2. In order to make the measuring circuit 1 operate in such a manner it is necessary to describe the test pattern 15 having a construction shown in FIG. 2(a) and (b).
In the conventional device, the test pattern 15 involved in a material such as a card is decoded by a decoder such as a card reader, and the content thereof is stored in the memory. When the device is operated, the information at zero address of the "PAT" is read out from the memory by a controller (not shown), and input/output pins of the semiconductor device 2 and pins to be measured are designated, and each of the registers 9 to 13 in the measuring circuit 1 connected to each pin is set to a predetermined value (refer to step 16 of FIG. 3(b)). A voltage of a predetermined logic level is input to each input pin from each driver circuit 4, and it is judged by the comparator 5 whether a voltage of a predetermined logic level is obtained at each pin to be measured among the output pins, whereby it is judged whether the logical verification is normal or abnormal by the controller. At the same time, a current is input to the pin from the diode bridge circuit 6 so as to measure a high impedance state, and it is detected by the comparator 5 whether the voltage of the contact element 14 rises up to a predetermined value, whereby it is judged whether the high impedance state is normal or abnormal by the controller. Such an operation is repeated until reaching the final address, and the function measurement of the semiconductor device 2 is completed (refer to step 17 of FIG. 3(b)).
On the other hand, in a DC measurement, a current is input to the pin which is to be subjected to a DC measurement by the PMU 3, and the voltage obtained is measured (refer to step 18 of FIG. 3(a)). Thereafter, a voltage is input to the pin, and the current obtained is measured (refer to step 19 of FIG. 3(a)). Such an operation is repeated several times, and it is judged whether the electric characteristics are normal or abnormal.
Under the semiconductor device testing device of such construction, the function measuring circuit 1 is provided for each pin of the semiconductor device 2, thereby making it possible to conduct a rapid test at the same time for all pins by executing the test pattern 15.
In a DC measurement, however, there are only provided 1 to 4 PMU(s) 3, and the DC measurement must be conducted by using only these small number of PMUs. These small number of PMUs make it only possible to measure each pin successively, resulting in a disadvantage that the period of time for measurement increases with the increase of the pin number. Providing the PMUs 3 correspondingly to all the pins so as to solve this problem results in another problem that the device becomes expensive because of costly PMUs 3.
As another prior art showing a testing method of a tri-state output semiconductor memory device, there is Japanese Patent Publication No. Sho. 57-18593. In this prior art, a voltage of high or low logic level is applied to an output terminal of a tri-state output semiconductor memory device through an impedance, and in this state the voltage level of the output terminal is compared with the voltage of high or low logic level. The normality or abnormality of the semiconductor memory device is judged based on the output of the comparator.
Another prior art semiconductor testing device is disclosed in an article "Programmable Current Load" in a catalogue "Sentry 50 Product Description" of FAIRCHILD, 1983. In order to judge the output state of a device a load resistance Rx of any value is usually externally connected between the device to be tested and the comparator in the testing circuit. However, this article provides a circuit construction where a load resistance of any value can be set by providing a dynamic load circuit and programmably deciding the voltage and current values applied to the dynamic load circuit.